(1) Field of the Invention
This invention relates to a dynamic read-write random access memory, and more particularly to a dynamic read-write random access memory fabricated with conductor-insulator-semiconductor FETs in integrated circuit form which is so improved as to minimize the dissipation of electric energy stored in a nonselected memory cell.
(2) Description of the Prior Art
Various electric circuits such as a processor and a memory have come to be integrated on a semiconductor due to the prominent development of semiconductor techniques.
A dynamic read-write random access memory (herein after abbreviated as "a dynamic RAM"), is a kind of semiconductor memory allowing not only the reading but also the writing of data. It is adapted to have a large capacity because a memory cell for holding data (stored electric charge) is formed of a smaller number of transistors.
With the dynamic RAM, data is stored in the capacitor (or parasitic capacitor) of an MOS FET circuit. Data thus stored gradually dissipates with time. To avoid such a data dissipation, the dynamic RAM is provided with a refresh circuit (or sense amplifier) to refresh the data in the capacitor before the data is fully lost. The interval at which data is to be refreshed by the refresh circuit is largely affected by the period in which data is capable of being held in the capacitor.
As is well known, a dynamic RAM of the above-mentioned type usually comprises a plurality of memory cells arranged in the matrix form; a plurality of address lines (rows) enabling data to be read out of memory cells belonging to a row selected or enabling data to be written therein; a plurality of data lines (columns) enabling data to be read out of a selected memory cell or to be written therein; data line-selecting transistors connected between the data lines on one hand and the input and output circuits on the other; sense amplifiers (refresh circuits); and other circuits.
This is well understood from the U.S. Pat. Nos. 3,765,003; 3,774,176; 3,969,706; 3,778,783 and 3,778,784 and the Japanese patent disclosures Nos. 51-74,535; 51-137,339; 51-122,343 and 46-3006.
When data is read out of a selected memory cell through a data line and an output circuit, or when data is written in a selected memory cell through an input circuit and a data line, a data line-selecting transistor is first changed from the OFF state to the ON state and then from the ON state to the OFF state.
Where, with the prior art dynamic RAM, data of "0" (corresponding to the referential voltage V.sub.SS) was read out of a memory cell, the potential of a selected date line sometimes presented a deviation .DELTA.V from the referential power source potential V.sub.SS toward the negative side, causing said dynamic RAM to make an erroneous behavior. Namely, since the potential of the data line indicated a deviation .DELTA.V from the referential power source potential V.sub.SS toward the negative side, the gate of a MOS transistor constituting a nonselected memory cell storing data of "1" (corresponding to a positive potential V.sub.DD) indicated a higher potential than the terminal (source) of the transistor connected to the data line, and the MOS transistor which indicated a weak or strong inversion region was rendered conductive. As a result, the data of "1" stored in the nonselected memory cell dissipated in a far shorter time than that defined by the leak current of a PN junction. Eventually, the dynamic RAM erroneously behaved. Current running through the MOS transistor sometimes amounted to 10.sup.2 to 10.sup.7 times the leak current of the PN junction.
Deviation .DELTA.V of the potential of the data line from the referential power source potential V.sub.SS toward the negative side arises from the following facts:
(1) The electric energy of the data line discharged to the referential potential V.sub.SS is divided by a capacitance arising between the gate of the data line-selecting transistor and the data line when the data line-selecting transistor is turned off and by other parasitic capacitance accompanying the data line.
(2) When the data line is discharged, ringing arises by a combination of inductance and capacitance accompanying the data line.
The above-mentioned problem that the data line shows a deviation .DELTA.V from the referential power source potential V.sub.SS toward the negative side is caused not only by the "ON-OFF" operation of the data line-selecting transistor but also by another factor such is the "ON-OFF" operation of input and output circuits and a refresh circuit (sense amplifier). This problem further occurs not only when the MOS FET is of N type but also when the MOS FET is of P type. Further, the problem occurs not only when the memory cell is of one transistor/cell type but also when the memory cell is of three transistors/cell type or four transistors/cell type.